The present invention relates generally to network computing systems, and more specifically to systems and techniques for implementing an SMBus/I2C interface in a network computing system.
The System Management Bus (SMBus) is an industry standard bus that was originally developed for use in portable computers powered by a smart battery. For example, using the SMBus, intelligent charging circuitry may communicate with the smart battery to control the charging of the battery, and a processor included in the portable computer may communicate with the smart battery to determine the amount of charge on the battery. Accordingly, the SMBus provides a simple and inexpensive way for a smart battery in a portable computer to communicate with the rest of the computing system.
In recent years, the SMBus has also been used in AC-powered computers. This is because such computers have increasingly incorporated power management functions to enhance energy efficiency, and the SMBus provides a standard way to control and access information from power-related and other devices included in these computers during the execution of power management functions.
Generally, the SMBus is a 2-wire interface comprising an SCL line, upon which a clock signal is provided, and an SDA line, upon which a digital data signal is provided. Further, the SMBus uses the Inter-Integrated Circuit (I2C) bus communication protocol to pass commands and messages between “master” and “slave” devices on the 2-wire bus.
For example, FIG. 1 depicts a Read Byte Protocol (RBP) 100, which conforms to the SMBus specification. In the first byte of the RBP 100, i.e., a start condition 102 followed by a slave address 104, a master device asserts the address of a slave device on the bus, and then follows the slave address 104 with a write bit 106. Next, the slave device asserts an acknowledge bit 108 on the bus. The master device then delivers a byte-long command code 110, which is followed by another acknowledge bit 112 asserted by the slave device. In the next byte of the RBP 100, i.e., a start condition 114 followed by a slave address 116, the master device again asserts the address of the slave device, and then follows the slave address 116 with a read bit 118. This denotes a read operation from the address of the slave device. Next, the slave device asserts another acknowledge bit 120 and then returns a data byte 122. Finally, the master device asserts a not-acknowledge bit 124 to signify the end of the read operation and stop condition 126 to finish the transaction.
FIG. 2 is a timing diagram depicting signals on the SCL and SDA lines during execution of the above-described read-byte transaction. Specifically, FIG. 2 depicts a start condition at time T1 corresponding to, e.g., the start condition 114, that comprises a high-to-low logic level transition of the SDA line while the SCL line is at a high logic level; and, a stop condition at time T6 corresponding to, e.g., the stop condition 126, that comprises a low-to-high logic level transition of the SDA line while the SCL line is at the high logic level. FIG. 2 also depicts, between times T2 and T5, at least a portion of the data byte 122 (see FIG. 1) asserted by the slave device on the SDA line. In accordance with the SMBus specification, that portion of the data byte 122 changes state only when the SCL line is low, e.g., at times T2 and T5, and is stable and valid for the read operation between times T3 and T4 when the SCL line is high.
Although the SMBus has been successfully used for enabling communications with a smart battery in a portable computer, the SMBus has drawbacks when used in AC-powered computers that execute power management functions, i.e., when such computers are “sleeping.” For example, according to the SMBus specification, the minimum high period of the clock sign al on the SCL line is specified as 4.0 μs. For high speed computing systems that utilize such a clock signal, this means that the read operation performed between the times T3 and T4, as depicted in FIG. 2, must be completed within 4.0 μs. However, this timing constraint can be problematic, especially in computers that are sleeping.
For example, when a computer is sleeping, it may be in a suspended power state in which all power is removed except for that required to maintain the current operational state in memory. Further, in a networked computer that is sleeping, power may also be maintained to at least a portion of a network interface card incorporated therein. Moreover, the clock frequency of a processor may be reduced in a computer that is sleeping to further reduce power consumption in this mode.
Although the clock frequency of a processor operating under normal conditions may be sufficient to enable that processor to complete the above-described read operation within the requisite period of 4 μs, a computer that is sleeping with a reduced clock frequency maybe incapable of completing such a read operation on the SMBus. Further, such sleeping computers may be incapable of completing other operations as well as the read operation on the SMBus during minimum periods of the clock signal.
It would therefore be desirable to have improved systems and techniques for implementing an SMBus/I2C interface in a computer that executes power management functions. Such systems and techniques would enable a computer to successfully complete operations via the SMBus whether or not the computer is sleeping. It would also be desirable to have such system and techniques that can be easily implemented in a networked computing system.